Low-Power, Low-Voltage SRAM Circuits Design For Nanometric CMOS Technologies

Embedded SRAM memory is a vital component in modern SoCs. More than 80% of the System-on-Chip (SoC) die area is often occupied by SRAM arrays. As such, system reliability and yield is largely governed by the SRAM's performance and robustness. The aggressive scaling trend in CMOS device minimum feature size, coupled with the growing demand in high-capacity memory integration, has imposed the use of minimal size devices to realize a memory bitcell. The smallest 6T SRAM bitcell to date occupies a 0.1um2 in silicon area. SRAM bitcells continue to benefit from an aggressive scaling trend in CMOS technologies. Unfortunately, other system components, such as interconnects, experience a slower scaling trend. This has resulted in dramatic deterioration in a cell's ability to drive a heavily-loaded interconnects. Moreover, the growing fluctuation in device properties due to Process, Voltage, and Temperature (PVT) variations has added more uncertainty to SRAM operation. Thus ensuring the ability of a miniaturized cell to drive heavily-loaded bitlines and to generate adequate voltage swing is becoming challenging. A large percentage of state-of-the-art SoC system failures are attributed to the inability of SRAM cells to generate the targeted bitline voltage swing within a given access time. The use of read-assist mechanisms and current mode sense amplifiers are the two key strategies used to surmount bitline loading effects. On the other hand, new bitcell topologies and cell supply voltage management are used to overcome fluctuations in device properties. In this research we tackled conventional 6T SRAM bitcell limited drivability by introducing new integrated voltage sensing schemes and current-mode sense amplifiers. The proposed schemes feature a read-assist mechanism. The proposed schemes' functionality and superiority over existing schemes are verified using transient and statistical SPICE simulations. Post-layout extracted views of the devices are used for realistic simulation results. Low-voltage operated SRAM reliability and yield enhancement is investigated and a wordline boost technique is proposed as a means to manage the cell's WL operating voltage. The proposed wordline driver design shows a significant improvement in reliability and yield in a 400-mV 6T SRAM cell. The proposed wordline driver design exploit the cell's Dynamic Noise Margin (DNM), therefore boost peak level and boost decay rate programmability features are added. SPICE transient and statistical simulations are used to verify the proposed design's functionality. Finally, at a bitcell-level, we proposed a new five-transistor (5T) SRAM bitcell which shows competitive performance and reliability figures of merit compared to the conventional 6T bitcell. The functionality of the proposed cell is verified by post-layout SPICE simulations. The proposed bitcell topology is designed, implemented and fabricated in a standard ST CMOS 65nm technology process. A 1.2_ 1.2 mm2 multi-design project test chip consisting of four 32-Kbit (256-row x 128-column) SRAM macros with the required peripheral and timing control units is fabricated. Two of the designed SRAM macros are dedicated for this work, namely, a 32-Kbit 5T macro and a 32-Kbit 6T macro which is used as a comparison reference. Other macros belong to other projects and are not discussed in this document

Micromechanical Modeling of the Deformation and Damage Behavior of Al6092/SiC Particle Metal Matrix Composites

To enhance the performance and design of metal matrix composites, it is extremely important to gain a better understanding of how the microstructure influences the deformation and damage behaviour of metal matrix composites under different loading conditions. Finite element (FE) analysis can be used to collect certain micromechanical information of composites that is difficult to obtain from experiments. In this work, the effect of the distance between the SiC particles and the loading conditions on the deformation and damage behaviour of Al6092/SiC particle composites is investigated under different strain rates (i.e., 1x10-4 , 2x10-4 , and 4x10-4 s-1). A program is developed to generate the 2D micromechanical FE model with 17.5Vol. % SiC particles. Based on the scanning electron microscopy (SEM) images, the FE model contains four SiC particle sizes (3.1, 4.46, 6.37, and 9.98 μm) with various percentages, which are randomly distributed in the micromechanical Al6092 alloy matrix. User-defined field (USDFLD) subroutine was developed and implemented through Abaqus/Standard based on maximum principal stress and Rice-Tracey triaxial damage indicator to evaluate the formability of the aluminium matrix composite (AMC) and to predict the brittle and ductile fracture of the SiC particles and the aluminium matrix, respectively, under tensile and shear loads. The results showed that the distribution of SiC particles in Al matrix has a significant effect on the mechanical properties of Al6092/SiC 17.5 particle composites. The formability and damage behaviour of composites improve as particle distance increases and strain rate decreases under tensile and shear loading. The fracture initiation toughness of fine SiC particles is higher than that of coarse SiC particles